Combining the Forwarding with Delay Slots Operations to Avoid the Branch Misprediction Penalty in Superscalar Processors
Keywords:
Branch Misprediction Penalty, Clock Cycle Per Instruction (CPI), Control hazard Dynamic Branch Prediction Million Instruction Per Second (MIPSAbstract
Using pipeline system in modern possessors has contributed significantly to the development of processors performance by increasing its speed faster than before, where CPI approaches to 1, however, this technique accompanied many problems, one of them called Branch Misprediction penalty due to control hazard, most of them occurs when implementing dynamic branch prediction. For every five jump commands of a program there is jump command, which causes interruption of the execution of orders through pipeline systems. There are many proposed previews studies, such as Dynamic Branch Prediction and Control Speculation, NTB Branch Predictor: Dynamic Branch Predictor for High-Performance Embedded Processors. This paper presents a new mechanism to combine forwarding and delay slots together to avoid a Branch Misprediction Penalty in Superscalar Processors, it's got better results
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